`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:22:55 08/08/2011
// Design Name:   LEDglow
// Module Name:   F:/Source code/xilinx/FPGA_TEST/LEDglow/LEDglow/LEDglow_tb.v
// Project Name:  LEDglow
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: LEDglow
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module LEDglow_tb;

	// Inputs
	reg clk;

	// Outputs
	wire LED;

	// Instantiate the Unit Under Test (UUT)
	LEDglow uut (
		.clk(clk), 
		.LED(LED)
	);

	initial begin
		// Initialize Inputs
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end

always # 10 clk = ~clk;
 
endmodule

